This invention relates to memory devices capable of operating in a burst mode, and, more particularly, to a column address path for burst mode memory devices provide more optimum propagation of column addresses.
Memory devices, including a synchronous dynamic random access memory (SDRAM) 10 shown in FIG. 1, typically receive both a row address and a column address that specify where data are to be transferred to or from within the memory device. The row and column addresses are initially applied to an address register 12 through an address bus 14. The address bus 14 is generally coupled to a memory controller (not shown in FIG. 1). Typically, a row address is initially received by the address register 12 and applied to a row address multiplexer 18. The row address multiplexer 18 couples the row address to a number of components associated with either of two memory banks 20, 22 depending upon the state of a bank address bit forming part of the row address. Associated with each of the memory banks 20, 22 is a respective row address latch 26 that stores the row address, and a row decoder 28 that applies various signals to its respective array 20 or 22 as a function of the stored row address. The row address multiplexer 18 also couples row addresses to the row address latches 26 for the purpose of refreshing the memory cells in the arrays 20, 22. The row addresses are generated for refresh purposes by a refresh counter 30 that is controlled by a refresh controller 32.
After the row address has been applied to the address register 12 and stored in one of the row address latches 26, a column address is applied to the address register 12. The address register 12 couples the column address to a column address latch 40. In a normal operating mode, the column address is coupled through a burst controller 42 directly to an address buffer 44. However, in a burst operating mode, the burst controller 42 generates a sequence of column addresses starting at the column address applied to the burst controller 42 from the column address latch 40. For example, the burst controller 42 may operate in a xe2x80x9cburst 2xe2x80x9d mode, in which one additional column address is generated by the burst controller 42, a xe2x80x9cburst 4xe2x80x9d mode, in which three additional column addresses are generated by the burst controller 42, and a xe2x80x9cburst 8xe2x80x9d mode, in which seven additional column addresses are generated by the burst controller 42. The burst controller 42 may also operate in either of two burst modes, namely a serial mode, in which the addresses generated by the burst controller 42 are sequential, or an interleaved mode, in which the addresses generated by the burst controller are sequential except that only the least significant bit (LSB) toggles between each pair of even and odd addresses. As discussed in greater detail below, it is important that column addresses generated by the burst controller 42 be quickly coupled to the column address buffer 44 after the burst controller 42 receives the initial column address from the column address latch 40.
After the burst controller 42 applies a column address to the column address buffer 44 in either the normal mode or the burst mode, the column address buffer 44 applies the column address to a column decoder 48. As is well known in the art, the column decoder 48 applies various signals to respective sense amplifiers and associated column circuitry 50, 52 for the respective arrays 20, 22.
Data to be read from one of the arrays 20, 22 is coupled to the column circuitry 50, 52 for the arrays 20, 22, respectively. The data are then coupled to a data output register 56, which applies the data to a data bus 58. Data to be written to one of the arrays 20, 22 are coupled from the data bus 58 through a data input register 60 to the column circuitry 50, 52 where they are transferred to the arrays 20, 22, respectively. A mask register 64 may be used to selectively alter the flow of data into and out of the column circuitry 50, 52, such as by selectively masking data to be read from the arrays 20, 22.
The above-described operation of the SDRAM 10 is controlled by a command decoder 68 responsive to high-level command signals received on a control bus 70. These high level command signals, which are typically generated by a memory controller (not shown in FIG. 1), are a clock enable signal CKE*, a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, and a column address strobe signal CAS*, which the xe2x80x9c*xe2x80x9d designating the signal as active low. The command decoder 68 generates a sequence of control signals responsive to the command signals to carry out the function (e.g., a read or a write) designated by the command signals. These control signals, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of these control signals will be omitted. The high-level command signals are clocked into the command decoder 68 in synchronism with a clock signal CLK. The CLK signal, or internal clock signals (not shown) generated from the CLK signal, control the timing at which the control signals carry out their respective functions in the SDRAM 10. The control signals are preferably registered with both the rising and falling edges of the CLK signal (or internal clock signals) so that two operations are accomplished each period of the CLK signal. An SDRAM 10 operating in this manner is known as a xe2x80x9cdouble data rate DRAMxe2x80x9d because two bits of data are read from or written to the SDRAM 10 for each clock CLK pulse.
One conventional design for a portion of the burst controller 42 is illustrated in FIG. 2. The burst controller 42xe2x80x2 may include substantially more circuitry than is shown in FIG. 2, but this circuitry has been omitted in the interest of brevity because this additional circuitry is not particularly relevant to the problem that the disclosed invention is intended to solve. External column address signals XA9-XA0 (or XA less than 9:0 greater than ) are coupled to the SDRAM 10 through the address bus 14 (FIG. 1) and then through the address register 12 to the column address latch 40. As previously mentioned, the burst controller 42xe2x80x2 then outputs column address designated as IA less than 9:0 greater than  to the column address buffer 44. In the burst mode, bits IA less than 0 greater than  and IA less than 9:3 greater than  of the internal column address are generated differently from the remaining bits IA less than 1 greater than  and IA less than 2 greater than  of the internal column address. More specifically, the IA less than 0 greater than  and IA less than 9:3 greater than  bits are generated by coupling the external bits A less than 0 greater than  and A less than 9:3 greater than  from respective column address latches 40 through a respective column address path 90. The reason these bits are generated differently is that the maximum size of the burst is 8 bits, and 8 bits can be counted using three bits of the internal address, i.e., IA less than 2:0 greater than . The bits IA less than 9:3 greater than  of the internal column address are constant as the IA less than 2:0 greater than  bits are incremented by a count of either 2, 4 or 8, depending upon the length of the burst. The IA less than 0 greater than  bit selects whether an even or an odd-numbered column will be initially addressed, and it toggles with each edge of the CLK signal, assuming the SDRAM 10 is a double data rate SDRAM.
As mentioned above, in the burst mode, the IA less than 2 greater than  and IA less than 1 greater than  bits are incremented from their initial values for even column addresses under certain conditions. This incrementing is accomplished for the column address bits of the burst by adder logic circuits 100 and 102. Latched external address bits LA_S1 and LA_S2 are applied to an input of a respective multiplexer 110, 112. The other input of each multiplexer receives a respective set of bits from a burst counter 116. The burst counter 116 supplies the bits CNT1_INC and CNT2_INC for all column addresses of a burst after the first bit of the burst. Each multiplexer 110, 112 is controlled by a RDWRA signal that has a first logic level during the first bit of a burst and has a second logic level during the remaining bits of the burst. The multiplexers 110, 112 thus couple the input of respective drivers 120, 122 to the respective latched external address during the first bit of a burst, and then to the burst counter 116 during the remaining bits of the burst. The adder logic circuits 100, 102 receive a latched external address bits LA_S0 and a respective external address bit LA_S1 and LA_S2 from the drivers 120, 122 respectively. The adder logic circuits 100, 102 then output respective even address bits IAE1 and IAE2. The column address bits IAO1, IAE1, IAO2, and IAE2, as well as remaining bits of the column address are coupled to the outputs of the column address path 90, output the resulting bits IA less than 9:0 greater than  to the column decoder 48 (FIG. 1).
As previously mentioned, the columns in the memory banks 20, 22 are divided into even-numbered and odd-numbered columns. The IA less than 2 greater than  and IA less than 1 greater than  bits of each column address for the odd-numbered columns (in which the IA less than 0 greater than  bit is a xe2x80x9c1xe2x80x9d) in the first bit of each burst are generated directly from the XA less than 2 greater than  and XA less than 1 greater than  bits so that IA less than 2 greater than =XA less than 2 greater than  and IA less than 1 greater than =XA less than 1 greater than . The IA less than 2 greater than  and IA less than 1 greater than  bits of each column addresses for the even-numbered columns (in which the IA less than 0 greater than  bit is a xe2x80x9c0xe2x80x9d) in the first bit of each burst are generated by the adder logic circuits 100, 102.
In summary, the burst controller 42xe2x80x2 functions to make the internal address bit IA less than 1 greater than  equal to the external address bit XA less than 1 greater than  when the burst controller 42xe2x80x2 is operating in the burst 2 mode or the interleaved mode or when the external address bit XA less than 0 greater than  is xe2x80x9c0xe2x80x9d. The internal address bit IA less than 1 greater than  is equal to the complement of the external address bit XA less than 1 greater than  when the burst controller 42xe2x80x2 is operating in the interleaved mode and in either the burst 4 or 8 mode and the external address bit XA less than 0 greater than  is xe2x80x9c1xe2x80x9d. Similarly, the above-described circuitry functions to make the IA less than 2 greater than  bit equal to the external address bit XA less than 2 greater than  when the burst controller 42xe2x80x2 is operating in the burst 2 or burst 4 mode or the interleaved mode or when the XA less than 0 greater than  bit is xe2x80x9c0xe2x80x9d or the XA less than 1 greater than  bit is xe2x80x9c0xe2x80x9d. The internal address bit IA less than 2 greater than  is equal to the complement of the external address bit XA less than 2 greater than  when the burst controller 42xe2x80x2 is operating in the serial mode and in the burst 8 mode and the external address bits XA less than 0 greater than  and XA less than 1 greater than  are both xe2x80x9c1xe2x80x9d.
The major disadvantage of the circuitry used in the burst controller 42xe2x80x2 of FIG. 2 stems from the number of circuit components the external address bits must be coupled through to generate the internal address bits. Specifically, from the address latch 40, the LA_S1 signal for the even columns is coupled through the multiplexes 110, the driver 120, the adder logic 100. In contrast, the LA_S1 signal for the odd columns is coupled through only a multiplexer 110. A similar disparity exists between the LA_S2 signal for the odd columns and the LA_S1 signal for the even columns. As a result, the internal address bits IA less than 2:1 greater than  for the even columns reach the column decoder 44 (FIG. 1) substantially later than the internal address bits IA less than 2:1 greater than  for the odd columns. In addition to this lack of symmetry, the inherent delay in passing the latched address bits LA_S1 and LA_S2 through five circuit components unduly delays the time that the column decoder 44 can begin decoding a column address.
As the speed at which memory devices continues to increase, these delays in decoding, addresses can markedly slow the operating speed of memory devices. There is therefore need for a burst controller that is capable of outputting internal addresses with less delay than the prior art burst controller described above.
The present invention is directed to a method and system for predecoding memory addresses by generating a sequence of predecode signals based on the memory address, providing the sequence of predecode signals as a first set of activation signals, and based on the value of the memory address, either resequencing the sequence of predecode signals and providing the resequenced predecode signals as a second set of activation signals or providing the sequence of predecode signals as the second set of activation signals. The address predecoder includes a decoder having input terminals for receiving memory address signals and further having output terminals for providing predecode signals. Based on the column memory address signals, the decoder selects one of the output terminals on which to provide an active predecode signal. The address predecoder also includes a shifting circuit having inputs coupled to the output terminals of the decoder and control terminals for receiving shift control signals. The shifting circuit provides first and second sets of activation signals on respective output terminals. The first set of activation signals correspond to the predecode signals. In response to receiving inactive shift control signals, the shifting circuit provides a second set of activation signals corresponding to the predecode signals, and in response to receiving active shift control signals, the shifting circuit reorders the predecode signals into a shifted arrangement which are provided as the second set of activation signals.